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preliminary this is a product that has fixed target specifications but are subject ramtron in ternational corporation to change pending characterization results . 1850 ramtron drive, colorado springs, co 80921 (800) 545 - f - ram , (7 19) 481 - 7000 rev. 1.1 www.ramtron.com july 2011 page 1 of 13 fm 25 040c 4kb serial 5v f - ram memory features 4k bit ferroelectric nonvolatile ram ? organized as 512 x 8 bits ? high endurance 1 trillion (10 12 ) read/writes ? 36 year data retention at +75 ? c ? nodelay? writes ? advanced high - reliabil ity ferroelectric process very fast serial peripheral interface - spi ? up to 20 mhz maximum bus frequency ? direct hardware replacement for eeprom ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme ? hardware protection ? software pr otection low power consumption ? 250 ? a active current (1 mhz) ? 4 ? a (typ.) standby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green /rohs soic ( - g) description the fm 25 040c is a 4 - kilobit nonvolatile memory employing an advanced ferroelectric proc ess. a ferroelectric random access memory or f - ram is nonvolatile but operates in other respects as a ram. it provide s reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. t he fm 25 040c performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after it has been successfully transferred to the device. the next bus cycle may commence immediately without the need for data polling. the fm25 040c is capable of supporting up to 10 12 read/write cycles, or a million times more write cycles than eeprom . these capabilities make the fm 25 040c ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm25 040c provides substantial benefits to users of serial eeprom, in a hardware drop - in replacement. the fm25 040c uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. the specifications are guaranteed over an industrial temperature range of - 40c to +85c . pin configuration pin names function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage 5v vss ground ordering information fm25 040c - g green 8 green 8 cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 2 of 13 figure 1. block diagram pin descriptions pin name i/o description /cs input chip select. this active - low input activates the device. when high, the device enters low - power standby mode , ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inpu ts are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 20 mhz and may be interrupted at any time. /hold input hold : the /hold pin is used when the host cpu m ust interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /hold must occur while sck is low. /wp input write protect: this active - l ow pin p revents all write operations, including those to the status register. if high, write access is determined by the other write protection features, as controlled through the status register. a complete explanation of write protection is provided on page 6. si input serial input: all input data is driven to this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * si may be connected to so for a single pin data interface. so output serial output: so is the data output pin. it is driven actively during a read and remains tri - state at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so c an be connected to si for a single pin data interface since the part communicates in half - duplex fashion. vdd supply supply voltage: 5v vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 64 x 64 fram array 9 data i / o register 8 nonvolatile status register 2 wp cs hold sck so si www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 3 of 13 overview the fm 25 040c is a serial f - ram memory. the memory array is logically organized as 512 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 25 040c and a serial eeprom with the same pin - out relates to its sup er ior write performance. this makes the fm 25 040c a drop - in replacement for mos t 4kb spi eeproms that support m odes 0 & 3 . memory architecture when accessing the fm 25 040c , the user addresses 512 locations each with 8 data bits. these data bits are shifted se rially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code including the upper address bit, and a word address. the word address consists of the lower 8 - address bits. the comp lete address of 9 - bits specifies each byte address uniquely . most functions of the fm 25 040c either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation essentially is zero, beyond th e time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. that is, by the time a new bus transa ction can be shifted into the part, a write operation will be complete. this is explained in more detail in the interface section that follows. users expect several obvious system benefits from the fm 25 040c due to its fast write cycle and high endurance as compared with eeprom. however there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring mil liseconds to write is vulnerable to noise during much of the cycle. note that the fm 25 040c contains no power management circuits other than a simple internal power - on reset. it is the users responsibility to ensure that v dd is within datasheet tolerance s to prevent incorrect operation . it is recommended that the part is not powered down with chip enable active. serial peripheral interface C spi bus the fm 25 040c employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 mhz. this high - speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25 040c operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25 040c devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data - in, and data - out pins are common among all devices. the chip select and hold pins must be driven separately for each fm 25 040c device. for a microcontroller that has no dedicate d spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the /hold pin. figure 3 shows a configuration that uses only three pins . protoc ol overview the spi interface is a synchronous serial interface using clock and data lines. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm 25 040c w ill begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of each chip select. while there are f our suc h modes, the fm 25 040c supports m odes 0 and 3. figure 4 shows the req uired signal relationships for m odes 0 and 3. for both modes, data is clocked into the fm 25 040c on the rising edge of sck and data is expected on the first rising edge after /cs g oes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to the part. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. important: the /cs must go inactive (h igh) after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select. www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 4 of 13 figure 2. system configuration with spi port figure 3. sys tem configuration without spi port spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi modes 0 & 3 f m 2 5 0 4 0 c m o s i : m a s t e r o u t , s l a v e i n m i s o : m a s t e r i n , s l a v e o u t s s : s l a v e s e l e c t s o s i s c k c s h o l d f m 2 5 0 4 0 c s o s i s c k c s h o l d s p i m i c r o c o n t r o l l e r s s 1 s s 2 h o l d 1 h o l d 2 m i s o m o s i s c k m i c r o c o n t r o l l e r f m 2 5 0 4 0 c s o s i s c k c s h o l d 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 5 of 13 data transfer all data transfers to and from the fm 25 040c occur in 8 - bit groups. they are synchronized to the clock signal (sck) and they transfer most significant bit (msb) first. the serial input data is clocked in on the rising edge of sck. the serial data output is driven from the falling edge of sck . command structure there are six comm ands called op - codes that can be issued by the bus master to the fm 25 040c . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent data transfer. they perform a single function, such as, enabling a write operation. second are commands followed by one byte, either in or out. they operate on the status register. third are commands for memory transactions followed by address a nd one or more bytes of data . table 1. op - code commands name description op - code wren set write enable latch 0000 _ 0110b wrdi write disable 0000 _ 0100b rdsr read status register 0000 _ 0101b wrsr write status register 0000 _ 0001b read read memory data 00 00 _a 011b write write memory data 0000 _a 010b wren - set write enable latch the fm 25 040c will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status register and writing the memory . sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status regi ster, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. a write to the status register has no effect on the wel bit. completing any write operation will automatically clear the write - enable latch and prevent further w rites without another wren command. figure 5 below illustrates the wren command bus configuration . wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by readin g the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration . figure 6 . wrdi bus configuration figure 5 . wren bus configuration www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 6 of 13 rdsr - read status register the rdsr command allows the bus master to verify t he contents of the status register. reading status provides information about the current state of the write protection features. following the rdsr op - code, the fm 25 040c will return one byte with the contents of the status register. the status register is described in detail in the status register & write protection section . wrsr C write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /wp pin must be high or inactive. not e that on the fm 25 040c , /wp prevents wri ting to the status register and the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. the bus timing for rdsr and wrsr are shown below . figure 7. rdsr bus timing figure 8. wrsr bus timing status register & write p rotection the write protection features of the fm 25 040c are multi - tiered. first, a wren op - code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the /wp pin and the status register . when /wp is low, the entire part is write - protected. when /wp is high, the memory protection is subject to the status register. writes to the status r egister are performed using the wren and wrsr command s and subject to the /wp pin. the status register i s organized as follows . table 2. status register bit 7 6 5 4 3 2 1 0 name 0 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 7 are fixed at 0 and cannot be modified. note that bit 0 (/rdy in eeproms) is wired low since f - ram writes have no delay and the memory is neve r busy. all eeproms use ready to indicate whether a write cyc le is complete or not. the bp1 and bp0 bits control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. this bit is intern ally set by the wren command and is cleared by terminating a write cycle (/cs high) or by using the wrdi command . bp1 and bp0 are memory block write protection bits. they specify portions of memory that are write - protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 180h to 1ffh (upper ?) 1 0 100h to 1ffh (upper ?) 1 1 000h to 1ffh (all) www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 7 of 13 the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the m emory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the bp1 and bp0 bits allow software to selectively write protect the array. these settings are only used when the /wp pin is inactive and th e wren command has been issued. the following table summarizes the write protection conditions . table 4. write protection wel /wp protected blocks unprotected blocks status register 0 x protected protected protected 1 0 protected protected protected 1 1 protected unprotected unprotected memory operation the spi interface, with its relatively high maximum clock frequency, highlights the fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm 25 040c can perform sequential writes a t bus speed. no page register is needed and any number of sequential writes may be performed . write operation all writes to the memory array begin with a wren op - code. the bus master then issues a write op - code. part of this op - code includes the upper bi t of the memory address. bit 3 in the op - code corresponds to a8. the next byte is the lower 8 - bits of the address a7 - a0. in total, the 9 - bits specify the address of the first byte of the write operation. subsequent bytes are data and they are written seque ntially. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffh is reached, the counter will roll over to 000h. data is written msb first. unlike eeproms, any number of bytes can be written s equentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op - code operation . read operation after the falling edge of /cs, the bus master can issue a read op - code. p art of this op - code includes the upper bit of the memory address. the next byte is the lower 8 - bits of the address. in total, the 9 - bits specify the address of the first byte of the read operation. after the op - code is complete, the si pin is ignored. the bus master then issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1ffh is reached, the counter will roll over to 000h. data is read msb first. t he rising edge of /cs terminates a read op - code operation.. the bus configuration for read and write operations is shown below . hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master takes the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high while sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state . www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 8 of 13 figure 9. memory write figure 10. memory read endurance internally, a f - ram operates with a read and res tore mechanism . therefore, endurance cycles are applied for each access: read or write. the f - ram architecture is bas ed on an array of rows and columns. each access causes a cycle for an entire row. in the fm25 040c , a row is 64 bits wide. every 8 - byte boundary marks the beginning of a new row. endurance can be optimized by ensuring frequently accessed data is located in different rows. regardless, f - ram read and write endurance is effectively unlimited at the 20mhz clock speed. even at 2000 accesses per second to the same row, 15 years time will elapse before 10 12 endurance cycles occur . 0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 a 0 1 1 ms b byte address 7 6 5 4 3 2 c s sc k s i s o 1 6 0 7 ls b ms b ls b data out 0 7 hi - z 7 6 5 4 3 2 1 0 ls b 0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 a 0 1 0 ms b byte address 7 6 5 4 3 2 c s sc k s i s o 1 6 0 7 ls b ms b ls b data 7 6 5 4 3 2 1 0 0 7 hi - z www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 9 of 13 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +7.0v v in voltage on any pin with respect to v ss - 1.0v to +7.0v and v in < v dd +1.0v t stg storage temperature - 55 ? c to + 125 ? c t lead lead temperatu re (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwise specified ) symbol parameter min typ max units notes v dd main power supply 4.5 5.0 5.5 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 20.0 mhz 0.25 4.0 ma ma 1 i sb standby current 4 10 ? a 2 i li input leakage current ? 1 ? a 3 i lo output leakage current ? 1 ? a 3 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v oh output high voltage @ i oh = - 1 ma v dd C 0.8 - v v ol output low voltage @ i ol = 2 ma - 0.4 v v hys input hystere sis 0.05 v dd - v 4 notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v in or v out = v ss to v dd . 4. this parameter is periodically sampled and not 100% tested. applies only to /cs and sck pins. www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 10 of 13 ac parameters ( t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwise specified ) symbol parameter min max units notes f ck sck clock frequency 0 20 mhz t ch clock high time 22 ns 1 t cl clock low time 22 ns 1 t csu chip select setup 10 n s t csh chip select hold 10 ns t od output disable 20 ns 2 t odv output data valid 20 ns t oh output hold 0 ns t d deselect time 60 ns t r data in rise time 50 n s 1,3 t f data in fall time 50 n s 1,3 t su data setup time 5 ns t h data hold tim e 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 20 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. rise and fall times measured between 10% and 90% of waveform. 3. this parameter is character ized and not 100% tested. capacitance (t a = 25 ? c , f=1.0 mhz, v dd = 5v) symbol parameter max units notes c o output c apacita nce (so ) 8 pf 1 c i input c apacitance 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. ac test condit ions input pulse levels 10% and 90% of v dd input r ise and f all t imes 5 ns input and o utput t iming l evels 0.5 v dd output load capacitance 30 pf data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 18 - years @ + 75oc 36 - years www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 11 of 13 serial data bus timing /hold timing power cycle timing power cycle timing ( t a = - 40 ? c to + 85 ? c, v dd = 4.5v to 5.5v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access start 1 - m s t pd last access complete to v dd (min) 0 - ? s t v r v dd rise time 3 0 - ? s/v 1 t vf v dd fall time 10 0 - ? s/v 1 notes 1. sl ope measured at any point on v dd waveform . cs sck si so 1 / tck tcl tch tcsh todv toh tod tcsu tsu th td tr tf cs sck so hold ths thh thz tlz ths thh v d d m i n t p u v d d c s t v r t p d t v f www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 12 of 13 mechanical drawing (8 - p in soic - jedec standard ms - 012 , variation aa ) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xx xx xx= part number, p= package typ e (g=soic) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 25 040c , green soic package, year 2010, work week 51 fm 25 040c - g a 00002g1 ric10 51 xxxx xxx - p r ll llll l ricyyww p i n 1 3 . 9 0 0 . 1 0 6 . 0 0 0 . 2 0 4 . 9 0 0 . 1 0 0 . 1 0 0 . 2 5 1 . 3 5 1 . 7 5 0 . 3 3 0 . 5 1 1 . 2 7 0 . 1 0 m m 0 . 2 5 0 . 5 0 4 5 0 . 4 0 1 . 2 7 0 . 1 9 0 . 2 5 0 - 8 r e c o m m e n d e d p c b f o o t p r i n t 7 . 7 0 0 . 6 5 1 . 2 7 2 . 0 0 3 . 7 0 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25040C - 4kb 5v spi f - ram rev. 1.1 july 2011 page 13 of 13 revision history revision date summary 1.0 3/22/2011 i nitial release 1.1 7/18/2011 added esd ratings. www.datasheet.co.kr datasheet pdf - http://www..net/

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